International audienceVertical double-gate (DG) FinFETs fabricated on SOI wafers show good gate control, reasonable threshold voltage and high carrier mobility despite the absence of the top-gate. The 3D coupling effect between the two lateral-gates and the back-gate is investigated based on experimental and simulation results. We compare DG and triple-gate FinFETs with various fin widths. Front-channel characteristics are easily tuned by applied bias at the back-gate if the fin is not too narrow. We highlight that vertical DG FinFET is more appropriate device for dynamic threshold voltage adjustment than triple-gate FinFET. An analytical model is proposed to quantify the coupling effect in DG FinFET by solving 2D Poisson equation. The body...
This paper presents an extensive experimental study of the effective mobility in the long-channel un...
State-of-the-art SOI transistors require a very small body. This paper examines the effects of body ...
To continue the scaling of CMOS technology to 65 nm node and beyond, FinFET double-gate device struc...
International audienceVertical double-gate (DG) FinFETs fabricated on SOI wafers show good gate cont...
We examined the effects of device parameters on the transfer characteristics of triple-gate fin fiel...
In this work the corner effect sensitivity to fin geometry variation in multifin dual and tri-gate S...
In this work the corner effect sensitivity to fin geometry variation in multifin dual and tri-gate S...
Fin field effect transistors (FinFETS) are silicon-on-insulator (SOI) transistors with three-dimensi...
Three-dimensional (3D) statistical simulation is presented to propose using triple-gate (TG) fin fie...
In this work an attempt has been made to analyze the scaling limits of Double Gate (DG) underlap and...
Three-dimensional (3D) statistical simulation is presented to propose using triple-gate (TG) fin fie...
This paper presents a simple and accurate model for determining I on and Ioff of a double-gate FinFE...
A threshold voltage (Vth) controllable multigate FinFET on a 10-nm-thick ultrathin BOX (UTB) SOI sub...
In this paper, the combination of the Dynamic Threshold (DT) voltage technique with a non-planar str...
The double-gate (DG) MOSFETs have been identified in the International Technology Roadmap for Semico...
This paper presents an extensive experimental study of the effective mobility in the long-channel un...
State-of-the-art SOI transistors require a very small body. This paper examines the effects of body ...
To continue the scaling of CMOS technology to 65 nm node and beyond, FinFET double-gate device struc...
International audienceVertical double-gate (DG) FinFETs fabricated on SOI wafers show good gate cont...
We examined the effects of device parameters on the transfer characteristics of triple-gate fin fiel...
In this work the corner effect sensitivity to fin geometry variation in multifin dual and tri-gate S...
In this work the corner effect sensitivity to fin geometry variation in multifin dual and tri-gate S...
Fin field effect transistors (FinFETS) are silicon-on-insulator (SOI) transistors with three-dimensi...
Three-dimensional (3D) statistical simulation is presented to propose using triple-gate (TG) fin fie...
In this work an attempt has been made to analyze the scaling limits of Double Gate (DG) underlap and...
Three-dimensional (3D) statistical simulation is presented to propose using triple-gate (TG) fin fie...
This paper presents a simple and accurate model for determining I on and Ioff of a double-gate FinFE...
A threshold voltage (Vth) controllable multigate FinFET on a 10-nm-thick ultrathin BOX (UTB) SOI sub...
In this paper, the combination of the Dynamic Threshold (DT) voltage technique with a non-planar str...
The double-gate (DG) MOSFETs have been identified in the International Technology Roadmap for Semico...
This paper presents an extensive experimental study of the effective mobility in the long-channel un...
State-of-the-art SOI transistors require a very small body. This paper examines the effects of body ...
To continue the scaling of CMOS technology to 65 nm node and beyond, FinFET double-gate device struc...