BIMOS transistor in thin silicon film and new solutions for ESD protection in FDSOI UTBB CMOS technology

session 2: POwer Devices and ESD ProtectionInternational audienceThe purpose of this study is to evaluate the ESD protection behavior using BIMOS transistors integrated in ultrathin silicon film for 28 nm FDSOI UTBB high-k metal gate technology. Using as a reference our measurements in hybrid bulk structures we extend the BIMOS design towards the ultrathin silicon film. Evaluations are done based on 3D TCAD simulation with standard physical models using ACS method and quasi-static DC stress (AVS method)