On the TSV delamination risk dependence on TSV distance and silicon crystal orientation

Continuous downsizing and integration of various electrical features in micro-electric devices go along with an increase of electrical interconnections e.g. copper vias (vertical interconnect access) in BEoL-layers (back end of line) and through Silicon vias (TSV) for 3D IC integration. However, the large mismatch in thermal expansion between Copper TSVs and the surrounding Silicon generates remarkable risks for delamination between Copper and the adjacent seed layer as well as for damaging within redistribution layers of BEoL/RDL stacks on front and backside of the Silicon substrate. This is especially happening because of the popup effects during manufacturing of those structures as well as of pumping during thermal cycling tests. As a result, the use of copper TSVs generates novel challenges for reliability analysis and prediction, i.e. to manage multiple failure modes - interface delamination, cracking and fatigue in particular. FEA simulation results utilizing bi-material fracture mechanics approaches - cohesive surface contact method and interaction integral in particular - investigate dependences of cracking/delamination risks on the distance of adjacent TSVs and on the Silicon crystal orientation against the axis of pairs of TSVs