A switch-level test generation system

A switch-level test generation system for synchronous sequential circuits has been developed in which a new algorithm for switch-level test generation and an existing fault simulator have been integrated. For test generation, a switch-level circuit is modeled as a logic network that correctly models the behavior of the switch-level including bidirectionality, dynamic charge storage, and ratioed logic. The algorithm is able to correctly generate tests for combinational and sequential circuits. Both nMOS and CMOS circuits can be modeled. In addition to the classical line stuck-at faults, the algorithm is able to handle stuck-open and stuck-closed faults on the transistors of the circuit. The time-frame based algorithm uses asynchronous processing within each clock phase to achieve stability in the circuit, and synchronous processing between clock phases to model the passage of time. The reverse time processing approach is applied to generate a test for a specified fault. Unlike earlier time-frame based test generators for general sequential circuits, the test generator presented uses the monotonicity of the logic network to speed up the search for a solution. Results on benchmark circuits show that the test generator outperforms an existing switch-level test generator both in time and space requirements. The test generator presented is the only known sequential switch-level test generator that is both fully automatic and provides an interface to an existing fault simulator