Design and FPGA implementation of digital transmission over severe ISI channels

Graduation date: 2013Inter-symbol interference is one of the major factors that make the realization of high-data-rate digital communications system complex. Current designs face two main challenges: how to efficiently utilize the available bandwidth and how to reduce the hardware complexity of the transmitter and receiver. Traditional solutions use a single-band architecture. When ISI is severe, it might require an equalizer to mitigate ISI, which usually results in a high complexity and power consumption. This thesis focuses on the analysis and FPGA implementation of a multiband communication architecture. This design ensures that the channel frequency response in each sub-band is approximately flat to avoid the need of an equalizer. Specifically, a four-band architecture is presented in detail, and this design is compared with the single-band approach.\ud First, basic theories are provided for convenience of understanding the major development in this thesis in terms of simulation and FPGA implementation. Then the channel characteristics, such as the frequency and impulse responses, are analyzed for a four-band architecture. The single- and four-band architectures are introduced separately and optimized in detail. The simulation results of both architectures are verified through FPGA implementation in the Xilinx Virtex5 development board. Finally, BERs of the two architectures are compared from both simulation and FPGA implementation results