IEEE 754 single precision standard compatible floating point processor implemented using silicon compiler technology

Graduation date: 1989Typically, a Floating Point processor will be\ud attached to a general-purpose digital computer to extend\ud and enhance its numeric processing capabilities. In this\ud thesis a multiple instruction, multiple data machine for\ud the addition, subtraction, multiplication and division of\ud floating point numbers is presented. The algorithms used\ud have been partitioned to optimise utilisation of the\ud parallel structure.\ud The processor was implemented and simulated on the\ud Silicon Compiler, a commercial computer-aided design tool.\ud The resulting chip is ready for fabrication and is 323*295\ud mils in size and can operate with a 5.8 MHz clock for a\ud two micron CMOS process