Synthesis of multi-rate arrays from directional uniform recurrence equations

Graduation date: 1990Advances in VLSI array processing have led to many new\ud parallel structures for real-time Digital Signal Processing (DSP)\ud applications. Among all the architectures, systolic arrays have played\ud an important role because systolic arrays have regular, local\ud interconnections with modular structure. In ordinary systolic arrays,\ud however, all processing operations and data transmissions use the same\ud time clock, which degenerates the speed performance when different\ud processing operations take different time to execute. Moreover, the\ud application scope of systolic arrays is restricted to Uniform\ud Recurrence Equations (URE), which is not applicable to all DSP\ud algorithms.\ud This thesis introduces a new type of array processor\ud architecture, Multi-rate Arrays (MRA). MRAs enhance the computation\ud speed by assigning different clocks to different processing operations.\ud They also enlarge the application scope of systolic arrays because MRAs\ud can be synthesized from Directional Uniform Recurrence Equations\ud (DURE), which is a more general form than URE.\ud The thesis first introduces the idea of MRA, demonstrates its\ud enhancement on speed performance over systolic arrays, and gives a\ud criterion in choosing different array structures. It then relates MRAs\ud with DURE by analyzing the characteristics of DURE and formulates a\ud systematic procedure for the synthesis of MRA from DURE.At last, it\ud demonstrates the synthesis of MRA by two examples in DSP\ud applications- --decimation filter and Toeplitz matrix factorization