Add to ORKGThe double-tree scan-path architecture, originally proposed for low test power, is adapted to simultaneously reduce the test application time and test data volume under external testing. Experimental results show significant performance improvements over other existing scan architectures
[[abstract]]We present efficient method for reducing test application time by broadcasting test conf...
This paper proposes a low power scan test scheme and formulates a problem based on this scheme. In t...
This paper proposes a generic multi-dimensional scan shift control concept for mul-tiple scan chain ...
In a scan-based system with a large number of flip-flops, a major component of power is consumed dur...
textAs the size and complexity of systems-on-a-chips (SOCs) continue to grow, test data volume and ...
This paper proposes a new DFT Architecture that contains three test scan modes. The test data could ...
textThis dissertation addresses the problem of excessive power dissipation during scan testing. Hig...
Shrinking technologies to deep sub-microns has raised demands for high quality testing. However, exc...
The first part of this thesis addresses the problem of power dissipation during test in the system i...
[[abstract]]Recently, power dissipation in full-scan testing has brought a great challenge for test ...
This paper presents segmented addressable scan (SAS), a test architecture that addresses test data v...
This paper presents a new technique for power minimization during test application in sequential cir...
states at circuit nodes may erroneously change. Further, BIST schemes with random test patterns may ...
Low power design techniques have been employed for more than two decades, however an emerging proble...
Scan-based testing methodologies remedy the testability problem of sequential circuits; yet they suf...
[[abstract]]We present efficient method for reducing test application time by broadcasting test conf...
This paper proposes a low power scan test scheme and formulates a problem based on this scheme. In t...
This paper proposes a generic multi-dimensional scan shift control concept for mul-tiple scan chain ...
In a scan-based system with a large number of flip-flops, a major component of power is consumed dur...
textAs the size and complexity of systems-on-a-chips (SOCs) continue to grow, test data volume and ...
This paper proposes a new DFT Architecture that contains three test scan modes. The test data could ...
textThis dissertation addresses the problem of excessive power dissipation during scan testing. Hig...
Shrinking technologies to deep sub-microns has raised demands for high quality testing. However, exc...
The first part of this thesis addresses the problem of power dissipation during test in the system i...
[[abstract]]Recently, power dissipation in full-scan testing has brought a great challenge for test ...
This paper presents segmented addressable scan (SAS), a test architecture that addresses test data v...
This paper presents a new technique for power minimization during test application in sequential cir...
states at circuit nodes may erroneously change. Further, BIST schemes with random test patterns may ...
Low power design techniques have been employed for more than two decades, however an emerging proble...
Scan-based testing methodologies remedy the testability problem of sequential circuits; yet they suf...
[[abstract]]We present efficient method for reducing test application time by broadcasting test conf...
This paper proposes a low power scan test scheme and formulates a problem based on this scheme. In t...
This paper proposes a generic multi-dimensional scan shift control concept for mul-tiple scan chain ...