The hardware implementation of private-key block ciphers

The National Institute of Standards and Technology (NIST) in the U.S. has initiated a process to develop a Federal Information Processing Standard (FIPS) for an Advanced Encryption Standard (AES) [1], to become the standard for private-key block encryption. The new encryption algorithm will be based on a 128-bit block size and the key size can be 128, 192, or 256 bits. AES will be a replacement for the Data Encryption Standard (DES) [2] which is based on a 64-bit block size and has a 56-bit key. In this regard, the agency has accepted candidate algorithm nominations for AES. -- One of the important evaluation criteria concerns the efficiency of the private-key block cipher from the hardware implementation perspective . RC6 [3] and CAST-256 [4] are among the fifteen candidate algorithms that have been accepted in the first round of the AES development phase. This thesis investigates the efficiency of these two AES candidates from the hardware implementation perspective with Field Programmable Gate Arrays (FPGAs) as the target technology. -- Our analysis and synthesis studies of both the ciphers suggest it would be desirable for FPGA implementations to have a simpler cipher design that makes use of simpler operations that not only possess good cryptographic properties, but also make the overall cipher design efficient from the hardware implementation perspective. As a result, the thesis also proposes a new private-key block cipher design that, not only is very efficient as far as its implementation in FPGAs is concerned, but at the same time is secure against the two most potent attacks that have been applied to block ciphers, namely, differential and linear cryptanalysis