s.RABILA2: an optimal VLSI routing algorithm with buffer insertion using iterative RLC model

Buffer insertion and wire sizing have been proven effective in solving the timing optimization problem in VLSI interconnect design. In this paper, we describe a graph-based maze interconnect routing algorithm for VLSI designs. An interconnect routing and buffer insertion with look-ahead algorithm is used to construct a maze routing path. Simultaneous routing with buffer insertion and wire sizing is applied, taking into account wire and buffer obstacles. An iterative RLC interconnect model is proposed to estimate interconnect delay. Experimental results proves the effectiveness of the look-ahead scheme and shows RLC delay model improvement in delay estimation