Vertically Stacked-NanoWires MOSFETs in a Replacement Metal Gate Process with Inner Spacer and SiGe Source/Drain
- Barraud, S.
- Lapras, V.
- Samson, M.,
- Gaben, L
- Grenouillet, L.
- Maffini-Alvaro, V
- Morand, Y.
- Daranlot, J
- Rambal, N.
- Previtalli, B
- Reboh, S
- Tabone, C
- Coquand, R
- Augendre, E
- Rozeau, O
- Hartmann, J,
- Vizioz, C
- Arvet, C
- Pimenta-Barros, P
- Posseme, N
- Loup, V
- Comboroure, C
- Euvrard, C
- Balan, V
- Tinti, I
- Audoit, G
- Bernier, N
- Cooper, D
- Saghi, Z
- Allain, F
- Toffoli, A
- Faynot, O
- Vinet, M
Publication date
December 2016
DOI Publisher
Institute of Electrical and Electronics Engineers (IEEE)Abstract
International audienceWe report on vertically stacked horizontal Si NanoWires (NW) p-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with inner spacers and SiGe source-drain (S/D) stressors. Recessed and epitaxially re-grown SiGe(B) S/D junctions are shown to be efficient to inject strain into Si p-channels. The Precession Electron Diffraction (PED) technique, with a nm-scale precision, is used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Finally, a significant compressive strain and excellent short-channel characteristics are demonstrated in stacked-NWs p-FETs
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