Procedural module generation for parameterized layouts

Procedural module generators which can generate fixed-coordinate layouts have been widely used in the design of analog integrated circuits. However, in order to estimate layout-induced parasitics during the circuit synthesis phase of an analog integrated circuit design flow, researchers have proposed the use of parameterized layouts in the design of analog circuits. This paper proposes techniques for designing parameterized layouts so that procedural module generators which are capable of generating parameterized layouts with different geometric structures can be constructed