Roundoff error sequences in fixed-point arithmetic digital processors

Three assumptions are normally made about roundoff error sequences in fixed-point arithmetic digital processors: all values of error, within the limits set by the roundoff process, have an equal probability of occurrence; they are random; and they are not correlated with any other signal or error sequence. The validity of these assumptions for digital filter realisations employing a signal wordlength in the range of 4 to 3 bits is examined. The investigation begins by using a fast Fourier transform algorithm to perform spectral analysis on roundoff error sequences when the test signal is a quantised sinusoid. It continues by comparing the variance of the error sequence measured at the output of various filter realisations with that theoretically predicted using the normal assumptions; this is done using random test sequences. It is shown that under certain conditions, for the signal wordlengths under consideration, each of the three assumptions can become invalid. In conclusion this work reports attempts to develop more accurate predictive noise models which only incorporate assumptions of greater validity