A parameterized T-S digital fuzzy logic processor: soft core VLSI design and FPGA implementation

Fuzzy Logic (FL) was developed by Zadeh to deal with the uncertainty involved in decision making and system modeling and control of real–life systems, and is an extension of the two–valued logic defined by the binary pair {false, true} or {0,1} to the entire continuous interval [0,1] of logic values between false=0 and true=1. The purpose of this paper is to design and implement a zero-order Takagi-Sugeno (T-S) parameterized digital fuzzy logic processor (DFLP), in which only the active rules (i.e. rules that give a non–null contribution for a given data set) are considered, at high speed of operation, without significant increase in hardware complexity. The DFLP discussed in this paper achieves an internal core processing speed of at least 100 MHz, and based on the chosen parameters is featuring four 12-bit inputs and one 12-bit output, with seven trapezoidal shape membership functions per input and a rule base of up to 2401 rules. The proposed architecture was implemented in a Field Programmable Gate Array (FPGA) chip with the use of a very high-speed integrated-circuit hardware-description-language (VHDL) and advanced synthesis and place and route tools