PVD process modelling and deposition into sub-micron features

Physical Vapour Deposition (PVD) is a thin film deposition technique used to deposit dim films for a wide variety of applications. One key application area is the microchip fabrication process where PVD is used to deposit the various layers of metal which interconnect die devices on the mictochip. This study focuses on this application area and the emphasis is placed on using PVD deposited matenals to coat and fill deep sub-mtcton vias and contacts. Through a combination of modelling, simulation, and experiment it is shown that PVD will remain the technology of choice up to and beyond 0 25|Jm technology. Chapter 1 introduces both the PVD process and microchip fabrication. The basic physics underlying PVD is studied and this discussion is extended to film growth kinetics, variations of the basic PVD process, and alternative / rival processes. The microchip fabrication process is discussed and the role PVD plays in the larger picture is highlighted. This is followed by a discussion on the direction the microchip fabrication industry is taking and what PVD must do to keep up. Chapter 2 looks at the PVD process in more detail. After introducing some commercially available sputter simulation packages, the development of a model and 3-D sputter simulation package is detailed. The sputter model / simulation is then used to investigate a number of key aspects of sputtering. The reactive sputtering process is discussed as is the sputter etch process and film uniformity as a function of process and hardware configurations. Chapter 3 looks at the barriers, liners and wetting layers typically used as part of the metallisation scheme. Emphasis is placed on achieving the required step coverage to achieve barrier integrity, reliable feature fill, and good yield The ionised metal PVD process is studied m detail and it js argued that this technique is probably the best available process for coating deep sub-micron features. Chapter 4 looks at the aluminium deposition process in detail in order to ascertain the best method of filling deep sub-micron high aspect ratio structures with aluminium Shrinking feature sizes means the low resistivity materials such as aluminium need to be used as the via and contact plug materials in order to maintain device optimum speed and performance. A number of different via fill schemes are presented. A remarkable bottom to top fill process is developed and explained with the help of a film growth simulation package. Chapter 5 follows on from chapter 4 and examines alternative fill processes using standard and collimated wetting layers. Detailed simulations which include the effect of wetting and seed layers are performed and the influences of these underlayers on the fill mechanism discussed. Chapter 6 examines the ionised PVD processing detail Film profiles over submicron features are studied as a function of the material fluxes to the substrate during deposition. Material re-deposition at the bottom of features due to the effects of ion bombardment is studied both experimentally and theoretically. It is found that re-deposition at the bottom of high aspect ratio features can be used to redistribute material to die lower sidewall, thus improving barrier integrity