This paper describes the principles of an original adaptive interconnect for a computational cluster. Torus topology (2d or 3d) is used as a basis but nodes are allowed to effectively migrate along the torus cycles. An optoelectronic scheme which makes such migrations possible with only local synchronisation is outlined. Between the instances of migration the interconnect behaves as a direct packet-routing network which constantly monitors its traffic parameters. A decentralised predictive algorithm is applied periodically to decide whether the current topology is consistent with the predominant traffic flow and if it is not, a reconfiguration to a better-matched topology occurs. We present simulation results that show that on some standard...
We present an overview of the application of machine learning for traffic engineering and network op...
Master of ScienceDepartment of Electrical and Computer EngineeringDon M. GruenbacherThe method for c...
This paper describes a router which is the key component of a scalable asynchronous on-chip and inte...
This paper describes the principles of an original adap-tive interconnect for a computational cluste...
A topology of point-to-point interconnections is an efficient way to network a cluster of computers ...
This article provides background information about interconnection networks, an analysis of previous...
Several coarse-grain reconfigurable architectures proposed recently consist of a large number of pro...
The 2012 IEEE International Parallel and Distributed Symposium (IPDPS), 21-25 May 2012, Shanghai, Ch...
This paper extends research into rhombic overlapping-connectivity interconnection networks into the ...
To realize the full potential of a high-performance computing system with a reconfigurable interconn...
In the early years of parallel computing research, significant theoretical studies were done on inte...
The Performance of a parallel algorithm depends in part on how the interconnection topology of the t...
AbstractThe interconnection design in computing clusters and data centers is expected to change sign...
The development of computers with hundreds or thousands of processors and capability for very high p...
Several coarse-grain reconfigurable architectures proposed recently consist of a large number of pro...
We present an overview of the application of machine learning for traffic engineering and network op...
Master of ScienceDepartment of Electrical and Computer EngineeringDon M. GruenbacherThe method for c...
This paper describes a router which is the key component of a scalable asynchronous on-chip and inte...
This paper describes the principles of an original adap-tive interconnect for a computational cluste...
A topology of point-to-point interconnections is an efficient way to network a cluster of computers ...
This article provides background information about interconnection networks, an analysis of previous...
Several coarse-grain reconfigurable architectures proposed recently consist of a large number of pro...
The 2012 IEEE International Parallel and Distributed Symposium (IPDPS), 21-25 May 2012, Shanghai, Ch...
This paper extends research into rhombic overlapping-connectivity interconnection networks into the ...
To realize the full potential of a high-performance computing system with a reconfigurable interconn...
In the early years of parallel computing research, significant theoretical studies were done on inte...
The Performance of a parallel algorithm depends in part on how the interconnection topology of the t...
AbstractThe interconnection design in computing clusters and data centers is expected to change sign...
The development of computers with hundreds or thousands of processors and capability for very high p...
Several coarse-grain reconfigurable architectures proposed recently consist of a large number of pro...
We present an overview of the application of machine learning for traffic engineering and network op...
Master of ScienceDepartment of Electrical and Computer EngineeringDon M. GruenbacherThe method for c...
This paper describes a router which is the key component of a scalable asynchronous on-chip and inte...