Application-driven co-design of fault-tolerant industrial systems

This paper presents a novel methodology for the HW/SW co-design of fault tolerant embedded systems that pursues the mitigation of radiation-induced upset events (which are a class of Single Event Effects - SEEs) on critical industrial applications. The proposal combines the flexibility and low cost of Software Implemented Hardware Fault Tolerance (SIHFT) techniques with the high reliability of selective hardware replication. The co-design flow is supported by a hardening platform that comprises an automatic software hardening environment and a hardware tool able to emulate Single Event Upsets (SEUs). As a case study, we selected a soft-micro (PicoBlaze) widely used in FPGA-based industrial systems, and a fault tolerant version of the matrix multiplication algorithm was developed. Using the proposed methodology, the design was guided by the requirements of the application, leading us to explore several trade-offs among reliability, performance and cost.This work makes part of RENASER project (ESP2007-65914-C03-03) funded by the 2007 Research National Plan of the Ministry of Science and Education in which context this work has been possible. The work presented here has been carried out thanks to the support of the research projects ’Aceleración de algoritmos industriales y de seguridad en entornos críticos mediante hardware’ (GV/2009/098) (Generalitat Valenciana) and ’Aceleración hardware de algoritmos industriales para el sector calzado’ (GRE08-P11) (University of Alicante)