Regulation versus Flow Control in NoC for Hard Real-time Systems: a Preliminary Case Study

Many-core architectures are promising candidates for the de- sign of hard real-time systems. Inter-core and core to external memory or peripheral communications use the Network- on-Chip (NoC). Such a NoC is typically composed of a set of routers. Internal organization of routers (mainly bu↵ers) as well as flow control aspects impact NoC performances and thus those of the many-core, including the Worst-Case Traversal Time (WCTT) which has to be guaranteed for hard real-time systems. In this paper we study the impact of flow control aspects on this WCTT. We consider two classes of NoC architectures, representative of the trend in the many-core market: Tilera Tile64-like NoCs where flow control is implemented at the router level and KalRay MPPA 256-like NoCs where flows are regulated at the source node level. We compute flow WCTT for different configurations and we show that there is no clear winner, since NoC performances highly depend on flow features