Role based shared memory access control mechanisms in NoC based MP-SoC

Security is becoming one of the main aspects of Multiprocessor System-on-Chip (MP-SoC) design. Software attacks, the most common type of attacks, mainly exploit vulnerabilities like buffer overflow. This is possible if proper access control to memory is absent in the system. In this paper, we propose three hardware based mechanisms to implement Role Based Access Control (RBAC) model in Network-on-Chip (NoC) based MP-SoC. According to our knowledge, our solutions are the first attempts to implement hardware based solutions based on RBAC model. All the three proposed mechanisms use Resource Access Manager (RMAN) in a shared memory MP-SoC. Processing element (PE) connected routers of the NoC are retrofitted with a module called Local Access Manager (LMAN). Three proposed access control mechanisms are central, hybrid, and local depending upon the location of the access control decisions taken. The proposed mechanisms ensure confidentiality and availability in the whole MP-SoC i.e they not only can detect and prevent unauthorized access attack but can prevent denial-of-service attack too. The largest area increase of a PE connected router (for hybrid case) is only 8.6% compared to a normal router. Experimental results show that in most of the cases, proposed mechanisms have similar average memory access latencies compared to a normal NoC. Only drawback of the three mechanisms is that they have a scalability limit and cannot be used for very large number of PEs. This drawback is also solved by modified local access control mechanism. We show the effectiveness of the modified local access control mechanism by implementing it in a massively parallel multi-application architecture called REDEFINE. We show that the modified local access control mechanism is scalable and causes acceptable area and power overhead. Synthesis results show that the REDEFINE router area and power is increased by only 1.13% and 1.3% respectively without deteriorating maximum frequency of operation. (C) 2015 Elsevier Ltd. All rights reserved