Add to ORKGWe present a technique for an all-digital on-chip delay measurement system to measure the skews in a clock distribution network. It uses the principle of sub-sampling. Measurements from a prototype fabricated in a 65 nm industrial process, indicate the ability to measure delays with a resolution of 0.5ps and a DNL of 1.2 ps
In this paper, we analyze the impact of process variations on the clock skew of VLSI circuits design...
International audienceThis paper presents a technique for precise crosstalk delay measurement based ...
In this paper we present a low cost, on-chip clock jitter digital measurement scheme for high perfor...
An all-digital on-chip clock skew measurement system via subsampling is presented. The clock nodes a...
Abstract—An all-digital on-chip clock skew measurement system via subsampling is presented. The cloc...
In this paper we present an on-chip clock jitter digital measurement scheme for high performance mic...
Clock skew is one of the significant issues of real-time networking. We have previously proposed a n...
A method of precise measurement of on-chip analog voltages in a mostly-digital manner, with minimal ...
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Comp...
,4bwract—Packetdelay and 10SStraces are frequently used by network engineers, as well as network app...
We present a low-cost on-line system for clock skew management in integrated circuits. Our Built-In ...
As integrated circuits are scaled down it becomes dif-ficult to maintain uniformity in process param...
This thesis investigates the use of averaging techniques in the development of clock ...
Clock-skew errors in time-interleaved ADCs importantly degrade the linearity of such converters. The...
With the scaling of CMOS technology, critical paths in digital circuits have become largely sensitiv...
In this paper, we analyze the impact of process variations on the clock skew of VLSI circuits design...
International audienceThis paper presents a technique for precise crosstalk delay measurement based ...
In this paper we present a low cost, on-chip clock jitter digital measurement scheme for high perfor...
An all-digital on-chip clock skew measurement system via subsampling is presented. The clock nodes a...
Abstract—An all-digital on-chip clock skew measurement system via subsampling is presented. The cloc...
In this paper we present an on-chip clock jitter digital measurement scheme for high performance mic...
Clock skew is one of the significant issues of real-time networking. We have previously proposed a n...
A method of precise measurement of on-chip analog voltages in a mostly-digital manner, with minimal ...
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Comp...
,4bwract—Packetdelay and 10SStraces are frequently used by network engineers, as well as network app...
We present a low-cost on-line system for clock skew management in integrated circuits. Our Built-In ...
As integrated circuits are scaled down it becomes dif-ficult to maintain uniformity in process param...
This thesis investigates the use of averaging techniques in the development of clock ...
Clock-skew errors in time-interleaved ADCs importantly degrade the linearity of such converters. The...
With the scaling of CMOS technology, critical paths in digital circuits have become largely sensitiv...
In this paper, we analyze the impact of process variations on the clock skew of VLSI circuits design...
International audienceThis paper presents a technique for precise crosstalk delay measurement based ...
In this paper we present a low cost, on-chip clock jitter digital measurement scheme for high perfor...