VLSI architecture for the Winograd Fourier Transform algorithm

A simple systolic architecture for the computation of the DFT using the Winograd Fourier Transform algorithm is presented. The architecture is shown to be problem-size independent and to satisfy the limited bandwidth constraint. By satisfying the above constraints, it is then shown to be naturally scalable within the limits allowed by the Winograd algorithm. The proposed architecture is compared with existing VLSI solutions using Winograd's technique. Lastly, the feasibility of deriving and using Winograd type algorithms for larger primes and prime-powers is studied