A 23Q MHz Half Bit Level Pipelined Multiplier using True Single Phase Clocking

An 8 bit by 8 bit signed two's complement pipelined multiplier in 1.6$_\mu$m N well CMOS, capable of throughputs o f 230 million multiplications per second, is described. A half bit level pipelined architecture, and the use o f true single phase clocked circuitry, are the key features of this design. Simulation studies indicate that the multiplier dissipates 540mW at 230MHz. The chip complexity i s 5176 transistors, and the area is 1.5mmx 1.4mm