Fully-differential 4 V-output range 14.5-ENOB step-wise ramp stimulus generator for on-chip static linearity test of ADCs

International audienceThis paper presents an on-chip step-wise ramp stimulus generator aimed at static linearity test applications for ADCs. The proposed ramp stimulus generator is based on a simple switched-capacitor integrator with a constant DC input. The integrator has been conveniently modified to produce a very small integration gain proportional to the capacitance difference of two capacitors, in such a way that the resulting step-wise ramp signal at the output has a step size below the LSB of the target ADC under test. In order to verify the feasibility of the proposed ramp generation technique, this paper details the design and experimental characterization of a proof-of-concept step-wise ramp generator in a 65 nm CMOS technology. Experimental results on 15 fabricated samples show an average linearity of 14.5 effective bits in a differential output range of ±2 V. Moreover, a discrete-time static linearity measurement strategy is proposed and, as a proof-of-concept validation, it is verified on an off-the-shelf 11-bit ADC using the fabricated generator samples. Experimental results show an accuracy of ±0.3 LSB in the measurement of the INL of the ADC under test