Smart routing logic for highly efficient readout of single photon avalanche diode arrays for time-resolved imaging

In recent years we assisted to a marked trend toward the development of large Single Photon Avalanche Diode arrays for Time-Correlated Single Photon Counting (TCSPC) measurements. Indeed, multichannel systems feature a higher counting capability compared to single-channel systems, thus permitting a speedup of TCSPC experiments. Above all, the exploitation of CMOS technology has paved the way to the integration of both detectors and electronics on the same chip, leading to systems with thousands of independent channels, but resulting in a trade-off with the performance. Even worse, the integration of a high number of channels has not led to a proportional increment of the measurement speed, thus limiting the advantages of a multichannel approach. In order to break the trade-off that currently affects TCSPC imagers, we propose a router-based architecture, which allows us to choose the best-suited technology for the design of different parts of the system, that is detectors, sensing electronics and time-measurement circuits. The system is based on a limited number of high-performance converters shared with a much larger detector array. During each excitation cycle, a smart routing logic selects a subset of the detectors carrying a valid signal and connects them to the external converters. Here we present a new routing algorithm exploiting digital gates distributed in a tree structure within a large 32x32 array. Our solution has a double advantage: it permits to maximize the measurement speed and to minimize the number of interconnections crossing the system, which is a major issue in dense multichannel arrays