Development, characterisation and simulation of wafer bonded Si-on-SiC substrates

Novel silicon-on-silicon carbide (Si/SiC) substrates are being developed in order to produce lateral power devices for harsh environment applications. Two methods of producing 100 mm Si/SiC substrates are detailed by wafer bonding silicon-on-insulator (SOI) wafers to semi-insulating 4H-SiC, then removing the SOI handle wafer and buried oxide. The final process includes a radical activation bonding process with low temperature processing, resulting in 97% yield. A uniform oxide layer at the Si/SiC interface of 1.4–1.8 nm is revealed, without voids, which minimises charge density at this interface. Capacitance-voltage (C-V) measurements of lateral metal-oxide-semiconductor capacitors (LMOS-Cs) are carried out on both processes revealing what appears to be an inversion from an n-type to a p-type like response in the 2 μm layers. Thinning the Si layers to 1 μm and making new LMOS-Cs, C-V responses show an improved n-type-like response, though frequency dispersion and incomplete accumulation remain. Finite element simulations showed that this effect could be reproduced by the introduction of interfacial charge at the two interfaces. Finally, while one possible explanation for fully inverting the C-V response of an n-type 2 μm Si layer on SiC was shown, the full understanding for this remains to be further studied