Small- and large-signal RF modeling of silicon-based substrates

Nowadays and especially for high-speed digital and RF applications, silicon substrate is not anymore a simple mechanical support for CMOS circuitry. The performance of CMOS integrated circuits (ICs) is quite dependent on the substrate electromagnetic and thermal characteristics. Accurate substrate models are required to properly predict and optimize high-speed and RF ICs. In this paper after reviewing the state-of-the-art substrates models, a simulation methodology that takes carrier dynamics into account, disallowing instantaneous changes in substrate carrier concentrations, and providing more accurate estimations of harmonic distortion (HD) components will be presented. Using this method, we simulated the HD components introduced in a CPW line on various flavors of Si-based substrates. The results are compared with measured HD components over a wide range of bias points and at three fundamental excitation frequencies from 900 MHz to 4 GHz. It is shown that carrier relaxation times are of first importance for understanding the HD levels introduced by Si-substrates at RF frequencies and above. Furthermore, characteristic dips in the extracted HD components, for increasing fundamental power, are evaluated and shown to be tightly linked to the position of the device’s DC bias voltage relative to the substrate’s flatband voltage. The new simulation tool is also capable of capturing these typical dips in the HD curves, and provides physical insight into the reasons behind their existence. Finally, the interest of the model to optimize the linearity of SOI RF switches will be presented