Algorithms of inserting boundary-scan circuit automatically

Boundary Scan is one of the most popular technique of DFT (design For Test) today. Although some tools can automatically insert and verify boundary-scan circuitry, but they are not easily used. So we desired a set tools. It can process the RTL and behavior VHDL files, distinguish the source files with boundary-scan circuitry, generate VHDL with IEEE 1149.1 compliant boundary scan circuitry. This paper describes the main algorithms of boundary-scan in detail: First, the tools scan the VHDL source code and obtain the pin and the pin types. Next consider about the bidirectional signal, 3-state signal which controlled pins BSCs (boundary-scan cells) configuration, process the clock pin in special. Finally generate the corresponding VHDL and BSDL files and test bench files with IEEE defined basic instruction