Design of elements for a self-timed fast packet switch

The authors discuss the design of self-timed bit-serial circuits. They approach this problem by introducing a novel signaling protocol and an architecture which assures that the pipelined stages in a bit-serial pipelined system can work with the maximum concurrency and spend minimum time in data transfer, so the highest throughput and hardware utilization can be achieved. Then the design of fast packet switching (FPS) elements based on this signaling protocol and the interconnection block architecture is presented. It is seen that the self-timed fast packet switch composed of these elements has no synchronization requirement between switches and input, output ports, and offers the potential to allow each input and output port to work with different clock frequencies. An experimental two-input, two-output self-timed FPS chip using 1.2-μm CMOS technology is introduced