Behavior of Copper Contamination for Ultra-Thinning of 300 mm Silicon Wafer down to <5 μm

Bumpless interconnects and ultra-thinning of 300 mm wafers for three-dimensional (3D) stacking technology has been studied [1, 2]. In our previous studies, wafer thinning effect using device wafers less than 10 μm was investigated [3, 4]. There was no change for the retention time before and after thinning even at 4 μm in thickness of DRAM wafer [5]. In this study, the behavior of Cu contamination on an ultra-thin Si stacked structure was investigated. Thinned Si wafers were intentionally contaminated with Cu on the backside and 250 °C of heating was carried out during the adhesive bonding and de-bonding processing. An approximately 200 nm thick damaged layer was formed at the backside of the Si wafer after thinning process and Cu particle precipitates ranged at 20 nm were observed by cross-sectional transmission electron microscopy (X-TEM). With secondary ion mass spectrometry (SIMS) and EDX analyses, Cu diffusion was not detected in the Si substrate, suggesting that the damaged layer prevents Cu diffusion from the backside