USB2.0 high-speed device용 LINK와 이를 이용한 데이터 획득장치의 FPGA 구현

MasterA LINK(serial interface engine) for USB2.0 HS interface was implemented in FPGA by using Verilog code; the LINK in FPGA combined with a lab-made PHY ASIC chip was successfully applied to a data acquisition system that sends an external 16-bit parallel data serially to PC. The LINK is made up of four blocks: a packet encoder, a FSM, a packet decoder, and a FIFO. The data acquisition system works with the data bandwidth up to 30MB/sec at the bulk transfe