수신단 TIA 터미네이션 듀오바이너리 및 4-레벨 균형코딩 4b4w 송수신 회로

DoctorTwo transceiver circuits are proposed for low-energy and low-EMI single-ended memory interface; one is a low-energy single-ended duobinary transceiver circuit with a TIA RX termination and the other is a low-EMI 4b4w single-ended parallel transceiver circuit with four-level balanced coding. Firstly, the low-energy single-ended duobinary transceiver is proposed for the point-to-point DRAM interface with an energy efficiency of 0.56 pJ/bit at 7 Gb/s. The transmitter power is reduced by decreasing the signal swing of transmission channel to 80 mV and replacing the multiplexer and the binary output driver in the transmitter by a duobinary output driver. A trans-impedance amplifier (TIA) is used at the receiver end of transmission channel. The TIA works as a receiver termination and also amplifies the input signal for subsequent processing. Analysis of the feedback loop delay and the nonlinearity of the TIA shows that they do not impose serious problems. The TIA output signal is applied to a duobinary-to-NRZ converter, which is implemented by using a direct feedback 1-tap DFE circuit with a tap-coefficient of 1.0. The reference voltage of the duobinary-to-NRZ converter is calibrated automatically to enable a small-swing signaling. The proposed transceiver chip in a 65 nm CMOS process works at 4.5 Gb/s with a 3" FR4 microstrip line, and at 7 Gb/s with a 0.6" FR4. Secondly, the low-EMI four-bit four-wire (4b4w) single-ended parallel transceiver is proposed for the point-to-point DRAM interface with the H-field peak reduction of 13.65 dB at 8 Gb/s. In the proposed parallel link, four-level balanced coding is employed to minimize simultaneous switching noise at transmitter, to utilize differential sensing without a reference voltage at receiver, and to maintain the same pin efficiency of 100% as the conventional single-ended parallel link. Electromagnetic interference (EMI) is also reduced because the sum of currents across all the wires zero with the proposed coding scheme. A modified capacitive pre-emphasis scheme for four-level signaling is also proposed at transmitter to compensate for inter-symbol interference by boosting the magnitude of the transition of the transmitter output signal with a different amount. The transmitted four-level signals are recovered by the differential comparators with an offset compensation and the simple decoder at receiver. The proposed transceiver chip in a 65 nm CMOS process consumes 2.39 pJ/bit with a 1.2 V supply and a 2" FR4 channel at 8 Gb/s