A 0.1-2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS

A 100-MHz-2-GHz closed-loop analog in-phase/quadrature correction circuit for digital clocks is presented. The proposed circuit consists of a phase-locked loop-type architecture for quadrature error correction. The circuit corrects the phase error to within a 1.5 degrees up to 1 GHz and to within 3 degrees at 2 GHz. It consumes 5.4 mA from a 1.2 V supply at 2 GHz. The circuit was designed in UMC 0.13-mu m mixed-mode CMOS with an active area of 102 mu m x 95 mu m. The impact of duty cycle distortion has been analyzed. High-frequency quadrature measurement related issues have been discussed. The proposed circuit was used in two different applications for which the functionality has been verified