Tunable dielectric properties of TiO2 thin film based MOS systems for application in microelectronics

Post-deposition annealing (PDA) is an inherent part of a sol-gel fabrication process to achieve the optimum device performance, especially in CMOS applications. Annealing removes the oxygen vacancies and improves the structural order of the dielectric films. The process also reduces the interface related defects and improves the interfacial properties. Here, we applied a sol-gel spin-coating technique to prepare high-k TiO2 films on the p-Si substrate. These films were fired at 400 degrees C for the duration of 20, 40, 60 and 80 min to know the effects of annealing time on the device characteristics. The current-voltage (l-V) and capacitance-voltage (C-V) characteristics of annealed TiO2 films were examined in All TiO2/p-Si device configuration at room temperature. The 60 min annealed film gives the optimum performance and contained 69.5% anatase and 39.5% rutile phase with refractive index 2.40 at 550 nm. The C-V and I-V characteristic showed a significant dependence on annealing time such as variation in dielectric constant and leakage current. This allows us to tune the various electrical properties of MOS systems. The accumulation capacitance (C-ox), dielectric constant (kappa) and the equivalent oxide thickness (EOT) of the film fired for 60 min were found to be 458 pF, 33, and 4.25 nm, respectively with a low leakage current density (3.13 x 10(-7) A/cm(2)) fired for 80 min at -1 V. The current conduction mechanisms at high bias voltage were dominated by trap-charge limited current (TCLC), while at small voltages, space charge limited current (SCLC) was more prominent. (C) 2016 Elsevier Ltd. All rights reserved