Design Architecture of a 2-D Separable Iterative Soft-Output Viterbi Detector

Viterbi detectors are widely used in all communication systems dealing with transmission and storage. In this paper, we develop the theory and design architecture for a 2-D separable iterative soft-output Viterbi detector (SISOVD) for applications in 2-D storage channels extending the original work from Wu et al. (IEEE Trans. Magn., vol. 39, no. 4, pp. 2115-2120, Jul. 2003). The contribution of this paper is twofold. First, we design a non-binary soft Viterbi detector that will be used as the core engine for the SISOVD and show its equivalence to the max-log-MAP algorithm implementation. We also study the performance of the algorithm through simulations under various design parameter constraints toward a systems architecture. Second, we propose a novel digital circuit that incorporates non-uniform quantization within a sliding block design framework. The proposed detector system architecture is tested within an field programmable gate array platform and proved to be efficient in terms of resource utilization, timing, and power compared with a conventional uniform quantizer with no signal-to-noise ratio performance degradation. It shows a 13.28% reduction in the total number of slice registers, 30.26% reduction in the slice lookup tables, 21.23% reduction in the critical path delay, and 14.84% reduction in the power consumption compared with the uniform quantizer