Add to ORKGAbstract—A new breed of processors like the Cell Broadband Engine, the Imagine stream processor and the various GPU processors emphasize data-level parallelism (DLP) and threadlevel parallelism (TLP) as opposed to traditional instructionlevel parallelism (ILP). This allows them to achieve order-ofmagnitude improvements over conventional superscalar processors for many workloads. However, it is unclear as to how much parallelism of these types exists in current programs. Most earlier studies have largely concentrated on the amount of ILP in a program, without differentiating DLP or TLP. In this study, we investigate the extent of data-level parallelism available in programs in the MediaBench suite. By packing instructions in a SIMD fashion, ...
AbstractWe analyse the capacity of different running models to benefit from the Instruction-Level Pa...
To achieve high performance, contemporary computer systems rely on two forms of parallelism: instruc...
The goal of this paper is to show that instruction level parallelism (ILP) and data-level parallelis...
Abstract—A new breed of processors like the Cell Broadband Engine, the Imagine stream processor and ...
Abstract—A new breed of processors like the Cell Broadband Engine, the Imagine stream processor and ...
This paper presents a framework for characterizing the distribution of fine-grained parallelism, dat...
Over the last decade, significant advances have been made in compilation technology for capitalizing...
This report presents a new architecture based on addding a vector pipeline to a superscalar micropro...
There have been many recent studies of the "limits on instruction parallelism" in applicat...
Complex media applications are becoming increasingly common on general-purpose systems such as deskt...
dataflow processors, superscalar processors, instruction scheduling, trace scheduling, software pipe...
(Submitted for Publication) The real-time execution of contemporary complex media applications requi...
The real-time execution of contemporary complex media applications requires energy-efficient process...
Multimedia applications are becoming increasingly important for a large class of general-purpose pro...
With the rise of chip-multiprocessors, the problem of parallelizing general-purpose programs has onc...
AbstractWe analyse the capacity of different running models to benefit from the Instruction-Level Pa...
To achieve high performance, contemporary computer systems rely on two forms of parallelism: instruc...
The goal of this paper is to show that instruction level parallelism (ILP) and data-level parallelis...
Abstract—A new breed of processors like the Cell Broadband Engine, the Imagine stream processor and ...
Abstract—A new breed of processors like the Cell Broadband Engine, the Imagine stream processor and ...
This paper presents a framework for characterizing the distribution of fine-grained parallelism, dat...
Over the last decade, significant advances have been made in compilation technology for capitalizing...
This report presents a new architecture based on addding a vector pipeline to a superscalar micropro...
There have been many recent studies of the "limits on instruction parallelism" in applicat...
Complex media applications are becoming increasingly common on general-purpose systems such as deskt...
dataflow processors, superscalar processors, instruction scheduling, trace scheduling, software pipe...
(Submitted for Publication) The real-time execution of contemporary complex media applications requi...
The real-time execution of contemporary complex media applications requires energy-efficient process...
Multimedia applications are becoming increasingly important for a large class of general-purpose pro...
With the rise of chip-multiprocessors, the problem of parallelizing general-purpose programs has onc...
AbstractWe analyse the capacity of different running models to benefit from the Instruction-Level Pa...
To achieve high performance, contemporary computer systems rely on two forms of parallelism: instruc...
The goal of this paper is to show that instruction level parallelism (ILP) and data-level parallelis...