In this paper a pipelined ring algorithm is presented for efficient computation of one and two dimensional Fast Fourier Transform (FFT) on a message passing multiprocessor. The algorithm has been implemented on a transputer based system and experiments reveal that the algorithm is very efficient. A model for analysing the performance of the algorithm is developed from its computation-communication characteristics. Expressions for execution time, speedup and efficiency are obtained and these expressions are validated with experimental results obtained on a four transputer system. The analytical model is then used to estimate the performance of the algorithm for different number of processors, and for different sizes of the input data
The Fast Fourier Transform appears frequently in scientific computing. Therefore it is desirable to...
In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inv...
This paper presents a new pipelined hardware archi-tecture for the computation of the real-valued fa...
In this paper a pipelined ring algorithm is presented for efficient computation of one and two dimen...
AbstractThe development of the fast Fourier transform (FFT) and its numerous variants in the past 30...
In this study we examine the effects of implementing the Radix 2, the Radix 4 and the Prime Factor F...
Many traditional algorithms for computing the fast Fourier transform (FFT) on conventional computers...
A parallel matrix multiplication algorithm is presented, and studies of its performance and estimati...
This paper presents the fastest fast Fourier transform (FFT) hardware architectures so far. The arch...
A parallel matrix multiplication algorithm is presented, and studies of its performance and estimati...
This paper presents the fastest fast Fourier transform (FFT) hardware architectures so far. The arch...
A generalized algorithm has been derived for the execution of the Cooley-Tukey FFT algorithm on a di...
This paper presents the fastest fast Fourier transform (FFT) hardware architectures so far. The arch...
Transputer technology and its use of parallel processing theories are investigated. The architecture...
This paper presents a new and optimal parallel implementation of multidimensional fast Fourier trans...
The Fast Fourier Transform appears frequently in scientific computing. Therefore it is desirable to...
In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inv...
This paper presents a new pipelined hardware archi-tecture for the computation of the real-valued fa...
In this paper a pipelined ring algorithm is presented for efficient computation of one and two dimen...
AbstractThe development of the fast Fourier transform (FFT) and its numerous variants in the past 30...
In this study we examine the effects of implementing the Radix 2, the Radix 4 and the Prime Factor F...
Many traditional algorithms for computing the fast Fourier transform (FFT) on conventional computers...
A parallel matrix multiplication algorithm is presented, and studies of its performance and estimati...
This paper presents the fastest fast Fourier transform (FFT) hardware architectures so far. The arch...
A parallel matrix multiplication algorithm is presented, and studies of its performance and estimati...
This paper presents the fastest fast Fourier transform (FFT) hardware architectures so far. The arch...
A generalized algorithm has been derived for the execution of the Cooley-Tukey FFT algorithm on a di...
This paper presents the fastest fast Fourier transform (FFT) hardware architectures so far. The arch...
Transputer technology and its use of parallel processing theories are investigated. The architecture...
This paper presents a new and optimal parallel implementation of multidimensional fast Fourier trans...
The Fast Fourier Transform appears frequently in scientific computing. Therefore it is desirable to...
In this paper we investigate various algorithms for performing Fast Fourier Transformation (FFT)/Inv...
This paper presents a new pipelined hardware archi-tecture for the computation of the real-valued fa...