In this paper, a new incremental algorithm for layout compaction is proposed. In addition to its linear time performance in terms of the number of rectangles in the layout, we also describe how incremental compaction can form a good feature in the design of a layout editor. The design of such an editor is also described. In the design of the editor, we describe how arrays can be used to implement quadtrees that represent VLSI layouts. Such a representation provides speed of data access and low storage requirements
Linear layouts are a simple and natural way to draw a graph: all vertices are placed on a single lin...
We present a generic algorithm to sequentially pave a rectangular area with smaller, fixed-surface, ...
We consider the two-dimensional compaction problem for orthogonal grid drawings in which the task is...
In this paper, a new incremental algorithm for layout compaction is proposed. In addition to its lin...
Symbolic layout and layout compaction are closely related topics. Symbolic layout captures more of a...
This paper presents a survey and a taxonomy of layout compaction algorithms, which are an essential ...
A compacter takes as input a VLSI layout and produces as output an equivalent layout of smaller area...
SIGLETIB: RO 1829 (1985,8) / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische Information...
A compacter takes as input a VLSI layout and produces as output an equivalent layout of smaller are...
This paper describes a new approach for IC layout and compaction. The compaction problem is translat...
General Purpose Layout System (GPLS) is proposed as a bidirectional layout conversion system. GPLS c...
Three new fast constraint graph generation algorithms, PPSS-1D, PPSS-1Dk and PPSS-2D, are presented ...
The work of F.M. Maley (Proc. Chapel Hill Conf. on VLSI, p.261-83, 1985) on one-dimensional compacti...
Thesis (Ph. D.)--University of Rochester. Dept. of Computer Science, 1984. Simultaneously published ...
Memory compaction is a technique for reclaiming cells containing garbage that are scattered over the...
Linear layouts are a simple and natural way to draw a graph: all vertices are placed on a single lin...
We present a generic algorithm to sequentially pave a rectangular area with smaller, fixed-surface, ...
We consider the two-dimensional compaction problem for orthogonal grid drawings in which the task is...
In this paper, a new incremental algorithm for layout compaction is proposed. In addition to its lin...
Symbolic layout and layout compaction are closely related topics. Symbolic layout captures more of a...
This paper presents a survey and a taxonomy of layout compaction algorithms, which are an essential ...
A compacter takes as input a VLSI layout and produces as output an equivalent layout of smaller area...
SIGLETIB: RO 1829 (1985,8) / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische Information...
A compacter takes as input a VLSI layout and produces as output an equivalent layout of smaller are...
This paper describes a new approach for IC layout and compaction. The compaction problem is translat...
General Purpose Layout System (GPLS) is proposed as a bidirectional layout conversion system. GPLS c...
Three new fast constraint graph generation algorithms, PPSS-1D, PPSS-1Dk and PPSS-2D, are presented ...
The work of F.M. Maley (Proc. Chapel Hill Conf. on VLSI, p.261-83, 1985) on one-dimensional compacti...
Thesis (Ph. D.)--University of Rochester. Dept. of Computer Science, 1984. Simultaneously published ...
Memory compaction is a technique for reclaiming cells containing garbage that are scattered over the...
Linear layouts are a simple and natural way to draw a graph: all vertices are placed on a single lin...
We present a generic algorithm to sequentially pave a rectangular area with smaller, fixed-surface, ...
We consider the two-dimensional compaction problem for orthogonal grid drawings in which the task is...