Current-Voltage Characteristics of Grain Boundaries in Cast Polycrystalline Silicon

Current-voltage ( I - U ) characteristics of grain boundaries (GBs) in cast polycrystalline silicon are reported. It is found experimentally that these I - U characteristics show a dependence on the polarity of the applied voltage. A model is developed to understand the I-U characteristics of GBs in semiconductors, taking into account the observed difference in doping concentration in the grains forming the GB. A single trap energy level is assumed for GB interface states. The potential barriers at GBs are estimated by calculating the increase in the density of filled interface states at the GB due to the applied bias. The I-U characteristics calculated through this model show the same general features as those of measured I-U characteristics