This paper describes a recently implemented program that very rapidly generates control paths for different variants of the constituent processing elements of a particular massively parallel machine, the NON-VON Supercomputer. The program, called PLATO, accepts as input a set of instruction opcodes, together with associated control information, and produces as output a functionally correct, highly area-efficient set of PLA's for the processing elements. One novel aspect of the program is its use of a channel routing algorithm to generate a Weinberger Array layout for the OR-plane of the PLA. By supporting extremely rapid generation of processing elements with different instruction sets, PLATO facilitates "rapid turnaround" architectural exp...
We consider a situation in which several sensors are used to collect data for signal processing sinc...
Making parallel systems easy to use, and parallel programs easy to write and run, are two major aims...
Hardware performance has been increasing through the addition of computing cores rather than through...
As part of our research on very high performance parallel architectures, we have been investigating;...
Recognition and representation of parallel processable streams in computer program
[Abstract] The widespread use of multicore processors is not a consequence of significant advances i...
We present new methods of configurations of computers said amorphous to equip them of capabilities o...
A compactor for VLSI layouts is an essential component in many CAD systems for VLSI design. It reduc...
International audienceThe increased capacity and enhanced features of modern FPGAs opens new opportu...
This manuscript is a synthesis of our research e ort since one full decade on the topic of low level...
Parallel machines have become more widely used. Unfortunately parallel programming technologies have...
The experimental program ¨SPC-PM Po 3D¨ is part of the ongoing research of the Chemnitz research gro...
Inter-node communication has turned out to be one of the determining factors of the performance on m...
Cataloged from PDF version of article.Stream processing is a computational paradigm for on-the-fly p...
The compelling next generation streaming applications containing several computationally intensive n...
We consider a situation in which several sensors are used to collect data for signal processing sinc...
Making parallel systems easy to use, and parallel programs easy to write and run, are two major aims...
Hardware performance has been increasing through the addition of computing cores rather than through...
As part of our research on very high performance parallel architectures, we have been investigating;...
Recognition and representation of parallel processable streams in computer program
[Abstract] The widespread use of multicore processors is not a consequence of significant advances i...
We present new methods of configurations of computers said amorphous to equip them of capabilities o...
A compactor for VLSI layouts is an essential component in many CAD systems for VLSI design. It reduc...
International audienceThe increased capacity and enhanced features of modern FPGAs opens new opportu...
This manuscript is a synthesis of our research e ort since one full decade on the topic of low level...
Parallel machines have become more widely used. Unfortunately parallel programming technologies have...
The experimental program ¨SPC-PM Po 3D¨ is part of the ongoing research of the Chemnitz research gro...
Inter-node communication has turned out to be one of the determining factors of the performance on m...
Cataloged from PDF version of article.Stream processing is a computational paradigm for on-the-fly p...
The compelling next generation streaming applications containing several computationally intensive n...
We consider a situation in which several sensors are used to collect data for signal processing sinc...
Making parallel systems easy to use, and parallel programs easy to write and run, are two major aims...
Hardware performance has been increasing through the addition of computing cores rather than through...