Engineered Si-based substrate for RF applications

The purpose of this master thesis is to design and fabricate Si-based RF substrates. A particular attention is given to the integration of the fabrication as a post-CMOS compatible process. Whereas recent results in literature are found for porous silicon substrates with great RF characteristics, their complete CMOS process integration and design-independence has not been achieved yet. The first part of this work focusses on trenched Si substrates. In Chapter 2 semiconductor simulations are realised in order to prove the substrates’ RF performances. The effective parameters are extracted from CPW simulations for different trench morphologies and bulk substrate characteristics. In Chapter 3 an integrated inductor is simulated on trenched substrates. The increase of the effective resistivity and the decrease of the permittivity demonstrate an improvement of the inductor’s Q factor and frequency bandwidth. In Chapter 4, metal-assisted chemical etching is demonstrated as a fast and low-cost fabrication process for the formation of deep trenches in Si substrates. A gold porous layer sputtering deposition technique is implemented that allows uniform etching of the trenches with a directional etch profile, perpendicular to the deposition surface. MACE etching parameters are studied thoroughly and are optimized to enable fast and uniform etching. The second part of this work consists in the porosification of silicon substrates without external power supply or front-side access, required by the classical anodization techniques. In Chapter 5 a process is defined for porous Si formation be MACE with metal nanoparticles. Metal NP formation is obtained by sputtering of ultra-thin gold films, followed by thermal annealing. The correlation between deposited metal thickness and nanoparticle size and surface coverage is illustrated. Porosification with NPs by MACE was performed. The results indicate a non-uniform etching rate and direction with a maximum etch depth of approximately 50 mm, not suitable for thick substrate porosification. In Chapter 6, an innovative fabrication process is proposed combining lateral porosification and galvanic etching of silicon. Deep trenches are etched by DRIE, however integration of MACE can be envisioned to improve the process’ cost and throughput. By engineered patterned deposition of Si3N4 and platinum layers, the substrate can be laterally and uniformly porosified by immersion in HF-based solution.Master [120] : ingénieur civil électricien, Université catholique de Louvain, 201