A 0.4V 0.08fJ/cycle Retentive True-Single-Phase-Clock 18T Flip-Flop in 28nm FDSOI CMOS

In this paper, we propose an 18-transistor (18T) True-Single-Phase-Clock (TSPC) Flip-Flop (FF) with static data retention based on two forward-conditional feedback loops, without increasing the clock load, in comparison to the baseline TSPC architecture. The proposed FF was implemented for ultra-low-voltage (ULV) operation in 28nm FDSOI CMOS. The performances of the proposed FF extracted from measurements of clock dividers are compared to reference designs including the conventional M-S FF, the baseline TSPC FF and a recently proposed retentive TSPC FF. Compared to the conventional M- S FF, the proposed FF shows respectively 5%, 60% and 30% improvements at 0.4V in maximum frequency, energy/cycle and leakage power