Add to ORKGUltra-low-voltage (ULV) operation of logic circuits is an interesting solution to reduce power consumption in digital circuits. However the always-on blocks at nominal Vdd are necessary for functionality or I/O communications, which induces complex timing closure. In this paper, we propose a 5.4fJ/cycle 0.4V to 1.2V level-shifting flip-flop in 28nm FDSOI, which simplifies the clock tree constraints between the power domains
In this paper, a flip-flop (FF) that minimizes the transition of internal nodes by using a dual chan...
The very low power and high speed dual VDD Flip Flop (FF) is proposed in this paper. The power reduc...
In this paper, we propose an 18-transistor true-single-phase-clock (TSPC) flip-flop (FF) with static...
Level converting flip-flops are critical elements in dual-VDD design for level conversion at the int...
The explosion market of the mobile application and the paradigm of the Internet of Things lead to a ...
In this paper, we propose an 18-transistor (18T) True-Single-Phase-Clock (TSPC) Flip-Flop (FF) with ...
In this paper, we propose a low-overhead solution to ensure contention-free data retention in clock-...
Abstract: We present ultra low power application, low power supply(vdd) of sub-threshold logic resul...
True Single Phase Clocked (TSPC) flip-flops (FF) are widely used in high-frequency dividers for thei...
Abstract: Power consumption is considered as one of the important challenge in modern VLSI design al...
Abstract — To achieve the most energy-efficient operation, this brief presents a circuit design tech...
In the present day microelectronics, supply voltage scaling has received an intense attention as an ...
The increasing demand of portable applications motivates the research on low power and high speed ci...
Power consumption plays an essential role in VLSI design. Earlier, the VLSI designers were more conc...
Two novel low power flip-flops are presented in the paper. Proposed flip-flops use new gating techni...
In this paper, a flip-flop (FF) that minimizes the transition of internal nodes by using a dual chan...
The very low power and high speed dual VDD Flip Flop (FF) is proposed in this paper. The power reduc...
In this paper, we propose an 18-transistor true-single-phase-clock (TSPC) flip-flop (FF) with static...
Level converting flip-flops are critical elements in dual-VDD design for level conversion at the int...
The explosion market of the mobile application and the paradigm of the Internet of Things lead to a ...
In this paper, we propose an 18-transistor (18T) True-Single-Phase-Clock (TSPC) Flip-Flop (FF) with ...
In this paper, we propose a low-overhead solution to ensure contention-free data retention in clock-...
Abstract: We present ultra low power application, low power supply(vdd) of sub-threshold logic resul...
True Single Phase Clocked (TSPC) flip-flops (FF) are widely used in high-frequency dividers for thei...
Abstract: Power consumption is considered as one of the important challenge in modern VLSI design al...
Abstract — To achieve the most energy-efficient operation, this brief presents a circuit design tech...
In the present day microelectronics, supply voltage scaling has received an intense attention as an ...
The increasing demand of portable applications motivates the research on low power and high speed ci...
Power consumption plays an essential role in VLSI design. Earlier, the VLSI designers were more conc...
Two novel low power flip-flops are presented in the paper. Proposed flip-flops use new gating techni...
In this paper, a flip-flop (FF) that minimizes the transition of internal nodes by using a dual chan...
The very low power and high speed dual VDD Flip Flop (FF) is proposed in this paper. The power reduc...
In this paper, we propose an 18-transistor true-single-phase-clock (TSPC) flip-flop (FF) with static...