Synthesis of reconfigurable multiplier blocks: part I: fundamentals

Reconfigurable Multiplier Blocks (ReMB) offer significant area, delay and possibly power reduction in time multiplexed implementation of multiple constant multiplications. This paper and its companion paper (subtitled Part II- Algorithm) together present a systematic synthesis method for Single Input Single Output (SISO) and Single Input Multiple Output (SIMO) ReMB designs. This paper presents the necessary foundation and terminology needed for developing a systematic synthesis technique. The companion paper illustrates the synthesis method through examples. The method proposed achieves reduced logic-depth and area over standard multipliers / multiplier blocks