A space-time modeler for systlic algorithms

Parallel processing is now a key architectural concept. One form aimed at exploiting massive parallelism is through systolic arrays. The design of systolic arrays via synthesis techniques is now well understood by the means of space and time transformations. This theory is currently being exploited in Newcastle by SADE, a design environment to generate systolic algorithms in an automatic manner. A Snapshot Generator and its implementation in software using C and XGKS is presented. This tool allows the simulation of a typical systolic array, by evolving its computation in space-time, directly from a description generated by existing synthesis techniques. The designer can time-step through his/her design and show how the various data streams actually flow across the resulting array. Such abilities often lead to intuitive insights and improved design before array construction