A reprogrammable computing platform for JPEG 2000 and H.264 SHD video coding
- Baruffa, G.
- Fiorucci, F.
- Frescura, F.
- Micanti, P.
- Verducci, L.
- Villarini, B.
- Baruffa, G.
- Fiorucci, F.
- Frescura, F.
- Micanti, P.
- Verducci, L.
- Villarini, B.
Publication date
January 2010
DOI Publisher
Institute of Electrical and Electronics Engineers (IEEE)Abstract
In this paper, the architecture of a DSP/FPGA based hardware platform is presented, which is conceived to leverage programmable logic processing power for high definition video processing. The system is reconfigurable and scalable, since multiple boards may be parallelized to speed-up the most demanding tasks. JPEG 2000 and H.264, both at HD and Super HD (SHD) resolutions, have been simulated and their performance found on the embedded processing cores. The results show that real-time, or near real-time, encoding is viable, and the modularity of the architecture allows for parallelization and performance scalability
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