Clock Distribution and Readout Architecture for the ATLAS Tile Calorimeter at the HL-LHC

The Tile Calorimeter (TileCal) is one detector of the ATLAS experiment at the large hadron collider (LHC). TileCal is a sampling calorimeter made of steel plates and plastic scintillators which are readout using approximately 10000 photomultipliers tubes. In 2024, the LHC will undergo a series of upgrades toward a high luminosity LHC (HL-LHC) to deliver up to 7.5× the current nominal instantaneous luminosity. The ATLAS Tile Phase II Upgrade will accommodate detector and data Acquisition (DAQ) system to the HL-LHC requirements. The detector electronics will be redesigned using a new clock distribution and readout architecture with a full-digital trigger system. After the Long Shutdown 3 (2024-2026), the on-detector electronics will transfer digitized hadron calorimeter data for every bunch crossing (~25 ns) to the Tile PreProcessors (TilePPr) in the counting rooms with a total data bandwidth of 40 Tb/s. The TilePPrs will store the detector data in pipeline memories to cope with the new ATLAS DAQ architecture requirements and will interface with the front-end link exchange system and the first trigger level. The TilePPr boards will distribute the sampling clock to the on-detector electronics for synchronization with the LHC clock using high-speed links configured for fixed and deterministic latency. The upgraded readout and clock distribution strategy were fully validated in a demonstrator system using prototypes of the upgraded electronics in several test beam campaigns between 2015 and 2018.The Tile Calorimeter (TileCal) is one detector of the ATLAS experiment at the Large Hadron Collider (LHC). TileCal is a sampling calorimeter made of steel plates and plastic scintillators which are readout using approximately 10,000 PhotoMultipliers Tubes (PMTs). In 2024, the LHC will undergo a series of upgrades towards a High Luminosity LHC (HL-LHC) to deliver up to 7.5 times the current nominal instantaneous luminosity. The ATLAS Tile Phase II Upgrade will accommodate detector and Data AcQuisition (DAQ) system to the HL-LHC requirements. The detector electronics will be redesigned using a new clock distribution and readout architecture with a full-digital trigger system. After the Long Shutdown 3 (2024-2026), the on-detector electronics will transfer digitized data for every bunch crossing (~25 ns) to the Tile PreProcessors (TilePPr) in the counting rooms with a total data bandwidth of 40 Tbps. The TilePPrs will store the detector data in pipeline memories to cope with the new ATLAS DAQ architecture requirements, and will interface with the Front End Link eXchange (FELIX) system and the first trigger level. The TilePPr boards will distribute the sampling clock to the on-detector electronics for synchronization with the LHC clock using high-speed links configured for fixed and deterministic latency. The upgraded readout and clock distribution strategy was fully validated in a Demonstrator system using prototypes of the upgraded electronics in several test beam campaigns between 2015 and 2018