Influence of Process-induced Stress and Defects on Device Performance and Reliability in Nanoscale MOSFETs

DoctorAs the gate dimensions of MOSFET are continuously scaled down, the conventional SiO2-based transistor confronts problems such as the increase in gate leakage current, mobility degradation, and low reliability. Strain engineering is being widely accepted as a promising technique to improve CMOS performance with significant mobility enhancement. Meanwhile, high-k materials having a higher dielectric constant than SiO2 are adopted to reduce the gate leakage current. However, high-k materials have many drawbacks such as the instability of threshold voltage Vth, mobility degradation, and low reliability.This thesis investigates the influence of process-induced stress and defects on device performance and reliability in nanoscale MOSFETs. Using the influence of process-induced stress on device parameters, an electrical method of extracting mechanical stress in the channel is proposed. Furthermore, the hot-carrier degradation and bias temperature instability (BTI) of MOSFETs with high-k/metal gate stacks are evaluated.The shallow trench isolation (STI) process being used to isolate between Si active regions causes mechanical stress which can influence the properties of MOSFETs. A high density plasma chemical vapor deposition (HDP-CVD) STI process generates compressive mechanical stress in Si active regions while tensile mechanical stress is generated if a spin-on-glass (SOG)-filled STI process is used. The dummy active patterns which are used to reduce the micro-loading effect affect the mechanical stress induced by STI process, and an electrical method of extracting this mechanical stress is proposed. The proposed method requires only the maximum transconductance gm and measured subthreshold current Id(sub.), eliminating the effect of deviations of the mobility and effective channel length Leff that occurred in a previous method using mobility. In addition, it eliminates the measurement error due to the drain-induced barrier lowering (DIBL) effect in a previous method using Id(sub.).The main challenge in the successful integration of high-k oxides with metal gates is achieving a low Vth. To obtain an appropriate Vth, the La2O3 capping layer is used for n-MOSFETs. However, the change in capping layer thickness affects the device reliability. The hot-carrier degradation in n-MOSEFTs with high-k/metal gate stacks is monitored by measuring Vth, gm, and SS. As the thickness of the La2O3 layer increases, Vth degradation is enhanced regardless of whether the La2O3 layer is deposited above or below the HfSiO layer. The generation of interface traps induced by hot-carrier stress is intensified with an increase in the bottom capping layer thickness. On the other hand, the generation of oxide traps induced by hot-carrier stress is intensified with an increase in the top capping layer thickness.The NBTI degradation of p-MOSFETs with high-k/metal gate stacks is evaluated, and the characteristics of traps induced by NBTI stress are analyzed. The extracted NBTI lifetime is ~ 80 years for p-MOSFETs with SiON dielectric stacks and ~ 38 days for p-MOSFETs with high-k/metal gate stacks. The low frequency noise measurement indicates that a large amount of oxide traps are distributed in deeper high-k layer. The DCIV measurement indicates that the interface trap generation is dominant in p-MOSFETs with SiON dielectric stacks subjected to NBTI stress, but the oxide trap generations is dominant in p-MOSFETs with high-k/metal gate stacks subjected to NBTI stress. In experiments for NBTI recovery, ΔVth of recovery increases at Vg,rec higher than VFB because the generated oxide traps are distributed in the high-k layer. The extracted trap energy level in p-MOSFETs with high-k/metal gate stacks is 1.67 eV before NBTI stress and 1.59 eV after NBTI stress. This indicates that the position of oxide traps that participates in the tunneling process moves to deeper place in high-k layer after NBTI stress.In the actual circuits, MOSFETs operate under a dynamic mode with different biases. Hence, enhanced degradation of n-MOSFETs with high-k/metal gate stacks under channel hot-carrier (CHC)/gate-induced drain leakage (GIDL) alternating stress is investigated. CHC stress generates negative oxide charges while GIDL stress generates positive oxide charges in the gate oxide near drain region. These oxide charges degrade device reliability, and degradation is enhanced when CHC stress and GIDL stress are applied alternatively. The degradation under CHC/GIDL alternating stress is due to the neutral traps and interface traps, and increases with the increase in frequency