Validating Consistency between a Feature Model and its Implementation

MasterConsistency across different lifecycle artifacts is an important issue in software engineering. In Software Product Line Engineering (SPLE), validating consistency becomes even more complicated because product line assets have embedded variabilities. Commonality and variability (C&V) of a software product line (SPL) are usually captured using a feature model. Then, they are embedded into an implementation (i.e., asset code) using various techniques including preprocessor directives. However, the product line asset code often evolves without properly updating other lifecycle artifacts including the variability model, and verification of the consistency of C&V across different product line assets is a major challenge.In this thesis, I propose an approach to validating the consistency between C&V expressed in a feature model and C&V embedded in an implementation. With this approach, product line engineers can have a method for maintaining consistency across of SPL assets systematically. This method has been applied to the flash memory product line at Samsung Electronics Co. Ltd. and improvements have been made over the years based on the feedback