A Memory-Mapped Invert Coding Scheme for Phase-Change Memory

MasterPhase-change memory (PRAM) is expected to become a part of main memory subsystems as PRAM compensates for several weaknesses of DRAM such as standby power and scaling. However, PRAM suffers from major limitations related to write operations. Among them, PRAM’s poor write endurance can limit the device lifetime. This paper proposes a new Memory-Mapped Invert-Coding scheme to reduce the total of number of bit updates by applying invert code (IC) at a hybrid granularity with fine-grain IC mapped onto PRAM address space. We propose a DRAM/DRAM memory controller design to incorporate our solution and in which frequently accessed fine-grain IC is cached in DRAM. We provide an application-specific design-time solution that takes into account the bit updates reduction capability per memory region. Experimental results show that our methods achieves 9.4% more reduction in total bit updates over the baseline for only 1% additional PRAM area overhead