Reducing power with activity trigger analysis

Conference of ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2015 ; Conference Date: 21 September 2015 Through 23 September 2015; Conference Code:118396International audienceIn this paper we propose and implement a methodology for power reduction in digital circuits, closing the gap between conceptual (by designer) and local (by EDA) clock gating. We introduce a new class of coarse grained local clock gating conditions and develop a method for detecting such conditions and formally proving their correctness. The detection of these conditions relies on architecture characterization and statistical analysis of simulation, all done at the RTL. Formal verification is performed on an abstract circuit model. We demonstrate a significant power reduction from 33 to 40% of total power on a clusterized circuit design for video processing